A defective circuit on a wafer usually narrows a chip designer’s options. MIT Lincoln Laboratory is treating the defect map as an input to the wiring design. Its Quantum Microsystems platform tests the wafer before drawing custom connections, allowing those paths to skirt bad components. MIT identified the platform on November 12 as one of the laboratory’s three recipients of this year’s R&D 100 Awards.
The approach addresses an awkward physical boundary in quantum computing. Superconducting devices operate at cryogenic temperatures while control electronics can sit at room temperature. Conventional coaxial cables occupy space between the two. As a system grows, making those connections fit becomes a separate engineering problem from making any one chip work.
The laboratory combines semiconductor and superconducting chips on a common wafer. A decision-tree method chooses routes, and digital lithography forms the custom wiring layers. Closely spaced chips connect across a superconducting network. Flexible interconnects patterned by lithography take the place of individual coaxial cables. The laboratory says the assembly also allows a chiplet to be replaced or upgraded.
What a replaceable chip changes
Repairability changes the economics of integrating many devices. If one component needs replacing, the value of the rest of the assembly depends on whether engineers can retain its wiring and working chips. That makes yield after assembly and performance after a repair meaningful measures alongside chip density. The award recognizes the integration technology. MIT’s account leaves those production measures open for a foundry evaluating the platform.